System Verilog Code Digital Design

System Verilog Code Digital Design
· Create a package to support complex numbers. Recall that complex numbers have a real
and an imaginary component. Assume these components are 32-bit floating point numbers.
Your package should create a user-defined data type for complex numbers called complex,
so that users of the package can declare variables of type complex. It should also define the
following functions:
function complex AddComplex(input complex M, N);
Add two complex numbers, returning a complex number
function complex MultComplex(input complex M, N);
Multiply two complex numbers, returning a complex number
function complex CreateComplex(input shortreal RealPart, ImaginaryPart);
Create and return a complex number from two shortreal components (real and
imaginary)
function void PrintComplex(input complex C);
Accept a complex number and print its components using the format
(r: number, i: number) where each component is a shortreal
function void ComplexToComponents(input complex C, output shortreal
RealPart, ImaginaryPart);
Accept a complex number and return (as outputs) the components (real and imaginary)
Create a module that imports the package and demonstrates the use and correct behavior of
each of the functions.
Recall the rules for addition and multiplication of complex numbers:
(a bi) (c di) = (a c) (b d)i
(a bi) x (c di) = a x c (a x d)i (b x c)i (b x d)i
2 = (a x c – b x d) (a x d b x c)i
· create a pipelined version of (using carry save adders). There should be a pipeline register between each state to hold intermediate results as well as those portions of the original inputs that will be needed in subsequent stages. There should be a pipeline register after the final stage to keep outputs stable during one clock cycle. Create a testbench for your pipelined multiplier module. Use a queue to hold the stimulus (multiplier/multiplicand pairs) for all operations until their product has been produced and verified when it emerges from the pipeline.